1. Field of the Invention
The present invention relates to a delay element, a variable delay line, a voltage controlled oscillator, and the like. More specifically, the present invention relates to circuit elements capable of adjusting delay amount or frequency and capable of executing temperature compensation. Further, the present invention relates to a device such as a display device using those circuit elements.
2. Description of the Relates Art
A voltage controlled oscillator capable of changing the oscillation frequency by applied voltages can easily control the oscillation frequency, since it can generate control signals more easily than a current control type. Thus, such voltage controlled oscillator is used widely. There are several techniques known as the voltage controlled oscillator. Among those, often used is a circuit in which a closed loop is formed by a plurality of units (each unit includes an inverter configured with a transistor and a function capable of adjusting delay of the converter), due to its simple circuit structure. The inverter configured with the closed loop can form an oscillator called a ring oscillator, which is formed to oscillate according to a feedback method. In the voltage controlled oscillators configured with the inverters, there exists a type of circuit which has a function of adjusting delay of the inverter achieved by a structure that has additional transistor added to a junction part between the inverter and a power supply, and takes a delay element configured by the inverter and the added transistor as one unit. With such circuit, the oscillation frequency can be changed by adjusting bias to the gate of the transistor that is connected to the power supply.
Japanese Unexamined Patent Publication 05-136693 (FIG. 1, paragraphs 0003-0004, 0009-0011, etc: Patent Document 1) discloses a phase lock loop that is configured by adding a technique for compensating the temperature characteristic to such voltage controlled oscillator. FIG. 63 is an illustration showing the phase lock loop depicted in Patent Document 1. The phase lock loop is configured with a voltage controlled oscillator 910, a phase comparator 904, a low-pass filter 905, and a selection circuit 906. Further, a potential compensating circuit 930 for fixing an oscillation clock when starting the oscillation is connected to the selection circuit 906. Furthermore, a temperature compensating circuit 920 is connected to the voltage control circuit 910.
The voltage controlled oscillator 910 is configured with a ring oscillator which obtains oscillation by feeding back output of serially connected odd-numbered stages of CMOS (Complementary Metal Oxide Silicon) transistors 911 to an input side. The frequency of an oscillation clock OCK is determined when an oscillation control voltage is supplied to gates of N-channel type MOS (Metal Oxide Silicon) transistors (referred to as “NMOS transistors” hereinafter) 912 which are connected to ground side of each CMOS transistor 911. The phase comparator 904 detects a phase difference between the oscillation clock OCK of the voltage controlled oscillator 910 and a specific-cycle reference clock RCK, and inputs a detection output PD that indicates phase difference between those clocks to the low-pass filter 905. The low-pass filter 905 eliminates a high-frequency component of the output PD of the phase comparator 904 indicating the phase difference between the oscillation clock OCK and the reference clock RCK, and inputs it to the selection circuit 906 as a first control voltage VC1. The first control voltage VC1 or a second control voltage VC2 is supplied from the selection circuit 906 to the gate of the MOS transistor 912 which determines the frequency of the oscillation clock OCK of the voltage controlled oscillator 910.
Further, P-channel type MOS transistors (referred to as “PMOS transistor” hereinafter) 913 are connected to the current source side of the respective CMOS transistors 911, and temperature compensating voltage VTC for turning on the PMOS transistors 913 in accordance with a temperature increase is applied to the gates of the PMOS transistors 913. The temperature compensating circuit 920 that generates the temperature compensating voltage VTC is configured with: a resistance 921 connected in series between the power supply grounds, and an NMOS transistor 922 whose gate is connected to the drain; a CMOS transistor 923 for receiving output of a junction point between the resistance 921 and the NMOS transistor 922; and a PMOS transistor 924 that is connected to the output side of the CMOS transistor 923, while its gate being connected to the drain. The output of the CMOS transistor 923 is supplied to the voltage controlled oscillator 910 as the temperature compensating voltage VTC. Therefore, when the driving capacity of the MOS transistor 922 becomes deteriorated by a temperature increase, voltage drop in the NMOS transistor 922 becomes significant. Thus, the potential at the junction point between the resistance 921 and the NMOS transistor 922 increased, so that the P-channel side of the CMOS transistor 923 is turned off and the N-channel side thereof is turned on. Thereby, the temperature compensating voltage VTC that is the output of the CMOS transistor 923 is pulled up. Because of the increase in the temperature compensating voltage VTC, on-resistance of the PMOS transistors 913 connected to each CMOS transistor 911 of the voltage controlled oscillator 910 is lowered. Therefore, deterioration in the driving capacity of the CMOS transistor 911 caused due to the temperature increase can be compensated, thereby suppressing an increase in the delay amount of each CMOS transistor 911. As a result, a large fluctuation in the frequency of the oscillation clock OCK can be prevented.
Further, the selection circuit 906 supplies, to the gates of the NMOS transistors 912, the first control voltage VC1 that fluctuates in accordance with the phase difference between the oscillation clock OCK and the reference clock RCK or the second control voltage VC2 of a fixed level. The first control voltage VC1 is obtained from the compared output PD of the phase comparator 904 which detects the phase difference between the oscillation clock OCK outputted from the voltage controlled oscillator 910 and the reference clock RCK, and it is inputted to the selection circuit 906. In the meantime, the second control voltage VC2 is obtained from the voltage compensating circuit 930 that is capable of obtaining a constant-level output regardless of fluctuations in the current source potential, and it is inputted to the selection circuit 906. The voltage compensating circuit 930 which generates the second control voltage VC2 of a constant level is configured with: an NMOS transistor 931 that is connected to the power supply side and has a power supply potential supplied to its gate; and two NMOS transistors 932, 933 connected in series on the ground side and have the gates connected to the drains. The voltage compensating circuit 930 outputs the potential of the junction point between the NMOS transistor 931 and the NMOS transistor 932 as the second control voltage VC2. With the use of such voltage compensating circuit 930, the potential on the power supply side of the NMOS transistor 932 shows a voltage higher by amount of threshold values of the NMOS transistors 932, 933 than the ground potential at all times. Therefore, the second control voltage VC2 obtained from the junction point between the NMOS transistors 931, 932 always keeps a constant level regardless of the fluctuation in the power supply potential.
However, in the delay element of the voltage controlled oscillator depicted in Patent Document 1, there are two sections that can be adjusted from outside for stabilizing the oscillation frequency with respect to changes in the temperature. Thereby, the structure becomes complicated. In addition, there are some issues as described in the followings.
A first issue is that the temperature compensation is insufficient, since the temperature compensation executed by the temperature compensating circuit of Patent Document 1 generates a temperature compensation voltage by utilizing only the difference between the temperature dependencies of the resistance and the diode-connected transistor. The temperature compensation becomes insufficient with this structure, due to the three following reasons.
The first reason is that there is a large difference in voltage-current characteristics of the resistance and the diode-connected transistor. Particularly, the diode-connected transistor is often used as a substitute for the resistance, however, linearity of the voltage and current is not good. Thus, the voltage determined by those two elements exhibits poor linearity for a change in the current caused due to the temperature.
The second reason is that the temperature dependency of the resistance and the diode-connected transistor varies depending on the voltage region. There is a small change in the temperature dependency of the resistance caused by the voltage. In the meantime, the temperature dependency of the transistor varies greatly depending on the voltages, since the temperature dependency of mobility and the temperature dependency of the threshold value have great roles, and the effects thereof are inverted from each other with respect to the temperatures. Therefore, changes in the voltages generated depending on the temperatures at both ends of the two elements vary, so that the correspondence between the changes in the temperature and the changes in the voltage becomes a nonlinear form. In some cases, the relation thereof becomes inverted, which makes it difficult to perform control thereon.
The third reason is that there is no accurate correspondence between the voltage for the temperature generated by the temperature compensating circuit configured with the resistance and the diode-connected transistor and the voltage for compensating the characteristic change caused due to the temperature change generated within the voltage controlled oscillator configured with the transistor. That is, the voltage controlled oscillator and the temperature compensating circuit have different temperature dependencies, so that the temperature compensation effect is not sufficient. Because of the three reasons, the temperature compensation executed with the technique of Patent Document 1 is insufficient.
The second issue is that there is a large chronological change in the performance, since it is necessary to apply biases (voltages) under different controls to both the power supply side and the ground side of the delay element. That is, a bias from the temperature compensating circuit is applied to the power supply side, and a bias from the potential compensating circuit is applied to the ground side. With this structure, the power supply side and the ground side are to be under completely different controls. Thus, the transistor (913 in FIG. 63) which receives the bias on the power supply side and the transistor (912 in FIG. 63) which receives the bias on the ground side are used under largely different bias conditions. As a result, deterioration states of the transistors on the current source side and the ground side vary greatly, so that deterioration caused due to one of the transistors changes the performance of the voltage controlled oscillator and affects the long-term reliability greatly. As described, the chronological change in the performance is significant.
Like the second issue, the third issue is caused due to the fact that the function of the potential compensating circuit for adjusting the frequency and the function of the temperature compensating circuit for compensating the temperature work at different sections of the delay element. That is, the technique of Patent Document 1 requires two sections that can be adjusted from outside provided within the delay element. As a result, the technique described above cannot be applied to a structure that has only one section that can be adjusted from outside provided within the delay element.
Further, in a case where there are two externally adjustable sections within the delay element, if both of the externally adjustable sections are configured to be controlled in the same manner in order to avoid the chronological change that is the second issue, it turns out as the same structure as the case of having only one adjustable section. Therefore, the technique described above cannot be applied to such case. That is, when it is structured to have a transistor for receiving the bias provided to the current source side and to the ground side, respectively, to be controlled simultaneously by respectively supplying a bias with which both transistors change in the same manner, there is only one kind of bias that can be used practically. Therefore, the technique of Patent Document 1 cannot be applied. Furthermore, in a case where there are two externally adjustable sections within the delay element, both of the two adjustable sections are used. Thus, other adjustable functions cannot be added. Therefore, the technique is used only in a very limited condition.
The fourth issue is that there is no versatility in using the structure. That is, the delay element is restricted to be structured with an inverter and a transistor added to the inverter, and no other structure can be used.